Loopback or not?

Issues in design verification of high-speed serial I/O devices. The increasing data rate of high-speed I/O devices makes currently available measurement tools such as realtime oscilloscopes obsolete. Measuring jitter performance of prototyped physical layer ICs of 5 Gb/s will particularly become a critical problem using current-mainstream oscilloscope technology. Therefore, the architecture of oscilloscopes has to be changed from a high-speed ADCcentric to an equivalent-time (ET) sampling architecture in order to provide the capabilities necessary for measuring signal integrity at and above 5 Gb/s. It is well known that the ET sampling architecture has several disadvantages [1]: 1. An oscilloscope takes long measurement times to measure a timing jitter probability density function (PDF). Typically, 15 sec is required for measuring jitter in only a 7600-bit stream [2]. 2. Phase noise directly affects jitter performance, but an oscilloscope cannot provide the link between jitter performance in the time domain and the phase noise spectrum in the frequency domain, 3. An oscilloscope cannot be used to measure the jitter performance of very noisy CMOS circuits because it is too sensitive to noise. Issues in loopback testing in a high-volume manufacturing environment. For immature products containing multi-Gb/s physical layer circuits, a loopback test can be performed to screen bad devices. It is well known that this type of testing suffers for the following reasons: 1. If a loopback test is done using patterns that are toggled between ones and zeros at 3 Gb/s, 6 Gb/s and 10 Gb/s, it requires transmission lines with bandwidths of at least 6 GHz, 12 GHz, and 20 GHz, respectively. 2. The Tx performance may mask the performance of the Rx. 3. In testing of mature products, the loopback test tends to reject too many good devices. 4. Loopback testing provides us no scalability for larger channel counts. It is inappropriate to test 100 I/O channels using a loopback configuration.